application note an9046 assembly guidelines for du al power56 packaging by dennis lang introduction the fairchild ? dual power56 package is based on molded leadless packaging (mlp) technology. this technology has been increasingly used in packaging for power related products due to its low package height, excelle nt thermal performance with large thermal pads in the center of the package which solder directly to the printed wiring board (pwb). modularity in package design, single and multi-die packages, is within the capability of mlp technology. the dual power56 has two large die attach pads allowing direct soldering to the pwb for best thermal and electrical performance. these two pads are the co-packaged high and low side mosfets. the dual power56 is designed to be used in high current synchronous buck dc-dc circuits, saving board space and component count by integrating the high and low side mosfets into one package. figure 1 : bottom side view showing pads for dual power56. this application note focuses on the soldering and back end processing of the dual power56. board mounting the solder joint and pad design are the most important factors in creating a reliable assembly. the pad dimensions must be designed to allow for tolerances in pwb fabrication and pick and place, which are necessary for proper solder fillet formation. mlp packages, when the pre-plated lead-frame is sawn, show bare copper on the end of the exposed edge leads. this is normal, and is addressed by ipc jedec j-std-001c ?bottom only termination?. in practice it has been found that optimized pwb pad design and a robust solder process often yields solder fillets to the ends of the lead due to the cleaning action of the flux in the solder paste. figure 2 : exposed copper on package edge, with solder wetting after reflow, from singulation process. pwb design considerations any land pad pattern must take into account the various pwb and board assembly tolerances for successful soldering of the mlp to the pwb. these factors have already been considered for the recommended footprint given on the datasheet. it
is recommended the customer follow this recommended footprint to assure best assembly yield, thermal performance and overall system performance. pad finish the dual power56 is sold with a nipdau lead free lead finish. immersion silver, immersion nickel gold and organic surface protectant, osp are the pad finishes of choice for lead free processing. each finish has useful properties, and each has its challenges. it is beyond the scope of this paper to debate each system?s merits. no one finish will be right for all applications, but currently the most commonly seen in large scale consumer electronics, largely due to cost, is osp. a high quality osp, formulated for the rigors of lead free reflow, like enthone ? entek ? plus ht is recommended. pwb material it is recommended that lead free fr-4 is used in pwb construction. lower quality fr-4 can cause numerous problems with the reflow temperatures seen when using lead free solder. ipc-4101b ?specification for base materials for rigid and multilayer printed boards? contains further information on choosing the correct pwb material for the intended application. using vias with dual power56 often the designer will wish to place vias inside of the thermal pads. while this is acceptable, the user should realize that vias often create voiding, and is advised to carefully characterize the pwb and process designs with x-ray inspection to ensure there is not a voiding problem. there are several types of vias that can be used in pwb design. blind vias are not recommended due to the fact they often trap gases generated during reflow and yield high percentages of vo iding. solder mask can also be placed over the top of the via to prevent solder from wicking down the via. it has been shown in previous studies that this will create a higher incidence of voiding than an open through- hole or filled via. if through hole vias are used, a drill size of 0.3mm with 1 ounce copper plating yields good performance. with through-hole vias, solder wicking through the hole, or solder protrusion, must be considered. in high reliability applications, filled vias are the preferred due to lower incidences of voiding during reflow. the user can expect this approach to eliminate the stress riser created by a void at the edges of the via barrel. stencil design it is estimated that 60% of all assembly errors are due to paste printing. for a controlled, high yielding manufacturing pro cess, it is therefore the most critical phase of assembly. due to the importance of the stencil design, many stencil types have been characterized to determine the optimal stencil design for the recommended footprint pad, on a typical application board with organic surface protectant (osp) surface finish, thermal vias, on fr-4. so lder paste coverage for the thermal pads was printed ranging from 50-65% coverage. to allow gases to escape during reflow it is recommended that the paste be deposited in a grid allowing ?channels? for gases to vent. it was found that 40-60% solder coverage on the large ?s1/d2? pad yielded good void performance, while maintaining good standoff height. the paste was printed from a 5 mil thick stainless steel stencil. various different stencil apertures shapes can be used, but were not studied here. the paste is printed on the outer pins with a slightly reduced ratio to the pwb pad. per ipc-7525 ?stencil design guidelines? gives a formula for calculating the area ratio for paste release prediction: t w l w l walls aperture of area pad of area ratio area * ) * ( * 2 * = = l is the length, w the width, and t the thickness of the stencil. when using this equation, an area ratio >0.66 should yield acceptable paste release. the recommended stencil apertures can be found in the appendix.
figure 3: printed solder paste, 50% coverage. solder paste the dual power56 is a rohs compliant and lead free package. the lead finish is nipdau. any standard lead free no clean solder paste commonly used in the industry should work with this package. the ipc solder products value council has recommended that the lead free alloy, 96.5 sn/3.0au/0.5cu, commonly known as sac 305, is ??the lead free solder paste alloy of choice for the electronics industry?. type 3 no-clean paste, sac 305 alloy, was used for the construction of the boards studied to optimize the process. reflow profile the optimum reflow profile used for every product and oven is different. even the same brand and model oven in a different facility may require a different profile. the proper ramp and soak rates are determined by the solder paste vendor for their specific products. obtaining this information from the paste vendor is highly recommended. if one is using a kic ? profiler, downloading the latest paste library from kic ? will yield ramp rate and soak times at temperature for most commonly used solder pastes. using this data the software can optimize the zone set-points and speed. the fairchild ? dual power56 is rated for 260oc peak temperature reflow. below is a sample reflow profile used for building demonstration boards. attached in the appendix is a reflow profile example. this profile is provided for reference only; different pwbs, ovens and pastes will change this profile, perhaps dramatically. voiding voiding is a very controversial topic in the industry currently. the move to lead free solders has driven the need for intense study in the area of solders, solder joints and reliability effects. there are varying viewpoints on the effect of vias and allowable quantity. there are several types of voids; for simplicity in th is applications note we will classify them into two categories, macro voids, and micro voids. macro voids could also be called process voids. macro voids are the large sized voids commonly seen on x-ray during inspection. these voids are due to process design and process control issues, or pwb design issues. all of the parameters discussed in this application note will effect macro- voiding. most standards that currently exist, such as ipc-610d specifically address void criteria for bga, and limit it to 25%. this standard is for macro voiding. there is currently no industry standard for macro voiding in mlp solder joints. fairchild ? has completed several reliability studies characterizing voiding in various types of components with large thermal pads, and the effect on reliability. it was found that components with
figure 4: x-ray image showing voiding caused by normal process variation during reflow. there are also several forms of micro-voiding, namely planar micro voids and kirkendall voids. the mechanism of void creation is different for each; however both are practically undetectable by x-ray inspection. both ty pes are also currently the subject of several in-depth studies; however, none have confirmed theories of creation. planar micro voids, or ?champagne voids? occur at the pwb land to solder joint interface. there are several theories on the mechanism that creates planar micro voids, but there is no industry consensus on the causal mechanism for this type of voiding. planar micro voids are a risk for reliability failures. kirkendall voids are created at the interface of two dissimilar metals at higher temperatures. in the case of solder attachments, at the pad to joint intermetallic layer. they are not due to the reflow process; kirkendall voids are created by electro- migration in assemblies that spend large amounts of time above 100oc. there is currently conflicting evidence whether kirkendall voids are a reliability risk or not. rework due to the high temperatures associated with lead free reflow, it is recommended that this component not be reused if rework becomes necessary. the dual power56 should be removed from the pwb with hot air. after removal, the dual power56 should be discarded. the solder remnants should be removed from the pad with a solder vacuum or solder wick, the pads cleaned and new paste printed with a mini stencil. localized hot air can then be applied to reflow the solder and make the joint. due to the thermal performance of this component, and the typical high performance pwb it will be mounted on, quite a bit of heat energy will be necessary. heating of the pwb may be helpful for the rework process. board level reliability as mentioned previously, per jdc-std-001d a solder fillet is not required on the side of the lead for this package. but it has been found through modeling and temperature cycling that a solder fillet on the lead end can improve reliability. an improvement of 20% can be expected with this fillet. it has also been found that the 20% reliability enhancement is attained even when the fillet only wets halfway up the side of the lead. the customer can expect to create reliability enhancing solder fillets through proper process design and control. as part of the standard reliability testing this package was temperature cycl ed from -10 to 100c. there could be no failures in the sample set at 1000 cycles to pass the test. works cited [1] aspandiar, raiyo, ?voids in solder joints,? smta northwest chapter meeting, september 21, 2005, intel corporation
[2] bryant, keith, ?investigating voids,? circuits assembly, june 2004 [3] comley, david, et al, ?the qfn: smaller, faster and less expensive,? chip scale review.com, august/september 2002 [4] englemaier, werner, ?voids in solder joints-reliability,? global smt & package, december 2005 [5] ipc solder products value council, ?round robin testing and analysis of lead free solder pastes with alloys of tin, silver and copper,? 2005 [6] ipc-a-610-d, ?acceptance of electronic assemblies,? february 2005 [7] ipc j-std-001d, ?requirements for soldered electrical and electronic assemblies,? [8] ipc-sm-7525a, ?stencil design guidelines,? may 2000 [9] jedec, jesd22-b102d, ?solderability,? va, sept. 2004 [10] syed, ahmer, et al, ?board level assembly and reliability considerations for qfn type packages,? amkor technology, inc., chandler, az applicable fsids: fdms9600s, fdms9620s
appendix note: the 8 edge pins and ?d1? high side solder ape rtures were not varie d, only the ?s1/d2? pad had solder area coverage varied. dimensioned stencil apertures, edge pins and ?d1? pad dimensions, the same for all three drawings:
dimensioned stencil apertur es, 40% large pad coverage:
dimensioned stencil apertur es, 50% large pad coverage:
dimensioned stencil apertur es, 60% large pad coverage:
reflow profile used for bu ilding demonstration boards.
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